The present invention relates to the improvement of a method of saving information from a processor and restoring the same to the processor, or sometimes to another processor, which is capable of reducing the time necessary for performing such saving and restoring of information. The present invention also concerns a processor system most suitable for implementation of the same method.
When a processor executes a command, and another command, which has the higher priority of execution, is issued, a processor must interrupt the execution of the command currently executed and start the execution of the another command. At that time, information existing within the processor upon receipt of the other command must be saved in an appropriate storage, and after completion of the execution of the other command, the saved information must be restored in the processor, or sometimes in another processor. These operations are known as a so-called interruption and interruption processing.
The following explanation will be made, taking a so-called coprocessor system as an example. There is already know a coprocessor system for a high-performance microcomputer system, in which, in addition to a main or host processor, there is provided a second processor, called a coprocessor, which executes external module functions, such as a floating-point calculation and a complicated input/output control including a direct memory access (DMA) control. With such a coprocessor system, not only the high performance of a microcomputer system is realized, but also the freedom or flexibility increases in the construction of a microcomputer system.
In such a coprocessor system, information of an internal status of a coprocessor must be saved in an appropriate storage, when a save command is issued by a host processor and restored therefrom, when a restore command is issued. One of conventional methods of saving and restoring is discussed, for example, in the article "The MC68881 Floating-point Coprocessor" by Clayton Huntsman et al on pp. 44 to 54 of "IEEE MICRO" Vol. 3, No. 6 (December 1983).
According to this publication, when a coprocessor receives a save command, the coprocessor discontinues the execution of a current command executed at that time irrespective of a time necessary for execution of the current command, and initiates the execution of the save command at once.
In such prior art, however, if the execution of a command is discontinued at random, a large amount of intermediate results of the execution of the command occurs, so that an amount of information transferred from the coprocessor to the storage increases. The large amount of information to be transferred causes a very long time of execution of the save command. As a result, the host processor must wait for a long time, until the execution of the save command is completed. This results in a degrading of the responsiveness of the microcomputer system.